Bump-on-Lead Flip Chip Interconnection

ABSTRACT

A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. The fusible portion melts at a temperature which avoids damage to the substrate during reflow. The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.

CLAIM OF DOMESTIC PRIORITY

The present application is a continuation of U.S. patent applicationSer. No. 13/464,979, filed May 5, 2012, which is a continuation of U.S.patent application Ser. No. 13/088,647, now U.S. Pat. No. 8,188,598,filed Apr. 18, 2011, which is a continuation of U.S. patent applicationSer. No. 12/716,455, now U.S. Pat. No. 7,973,406, filed Mar. 3, 2010,and reissued as U.S. Pat. No. RE44,431, which is a continuation of U.S.patent application Ser. No. 12/062,293, now U.S. Pat. No. 7,700,407,filed Apr. 3, 2008, and reissued as U.S. Pat. No. RE44,355, which is adivision of U.S. patent application Ser. No. 10/985,654, now U.S. Pat.No. 7,368,817, filed Nov. 10, 2004, which claims the benefit of U.S.Provisional Application No. 60/533,918, filed Dec. 31, 2003 and U.S.Provisional Application No. 60/518,864, filed Nov. 10, 2003.

FIELD OF THE INVENTION

The present invention relates to semiconductor packaging and,particularly, to flip chip interconnection.

BACKGROUND OF THE INVENTION

Flip chip packages include a semiconductor die mounted onto a packagesubstrate with the active side of the die facing the substrate.Conventionally, interconnection of the circuitry in the die withcircuitry in the substrate is made by way of bumps which are attached toan array of interconnect pads on the die, and bonded to a corresponding(complementary) array of interconnect pads (often referred to as“capture pads”) on the substrate.

The areal density of electronic features on integrated circuits hasincreased enormously, and chips having a greater density of circuitfeatures also may have a greater density of sites for interconnectionwith a package substrate.

The package is connected to underlying circuitry, such as a printedcircuit board (e.g., a “motherboard) in the device in which it isemployed, by way of second level interconnects (e.g., pins) between thepackage and the underlying circuit. The second level interconnects havea greater pitch than the flip chip interconnects, and so the routing onthe substrate conventionally “fans out”. Significant technologicaladvances have enabled construction of fine lines and spaces; but in theconventional arrangement space between adjacent pads limits the numberof traces than can escape from the more inward capture pads in thearray, and the fan out routing between the capture pads beneath the dieand the external pins of the package is conventionally formed onmultiple metal layers within the package substrate. For a complexinterconnect array, substrates having multiple layers may be required toachieve routing between the die pads and the second level interconnectson the package.

Multiple layer substrates are expensive, and in conventional flip chipconstructs the substrate alone typically accounts for more than half thepackage cost (about 60% in some typical instances). The high cost ofmultilayer substrates has been a factor in limiting proliferation offlip chip technology in mainstream products.

In conventional flip chip constructs the escape routing patterntypically introduces additional electrical parasitics, because therouting includes short runs of unshielded wiring and vias between wiringlayers in the signal transmission path. Electrical parasitics cansignificantly limit package performance.

SUMMARY OF THE INVENTION

According to the invention flip chip interconnect is accomplished byconnecting the interconnect bump directly onto a lead, rather than ontoa pad. The invention provides more efficient routing of traces on thesubstrate. Particularly, the signal routing can be formed entirely in asingle metal layer of the substrate. This reduces the number of layersin the substrate, and forming the signal traces in a single layer alsopermits relaxation of some of the via, line and space design rules thatthe substrate must meet. This simplification of the substrate greatlyreduces the overall cost of the flip chip package. The bump-on-leadarchitecture also helps eliminate such features as vias and “stubs” fromthe substrate design, and enables a microstrip controlled impedanceelectrical environment for signal transmission, thereby greatlyimproving performance.

In one general aspect the invention features a flip chip interconnectionhaving solder bumps attached to interconnect pads on a die and matedonto corresponding traces on a substrate.

In another general aspect the invention features a flip chip packageincluding a die having solder bumps attached to interconnect pads in anactive surface, and a substrate having electrically conductive traces ina die attach surface, in which the bumps are mated directly onto thetraces.

In general the bump-on-lead interconnection is formed according tomethods of the invention without use of a solder mask to confine themolten solder during a re-melt stage in the process. Avoiding the needfor a solder mask allows for finer interconnection geometry.

In some embodiments the substrate is further provided with a solder maskhaving openings over the interconnect sites on the leads. In someembodiments the substrate is further provided with solder paste on theleads at the interconnect sites.

In another general aspect the invention features a method for formingflip chip interconnection, by providing a substrate having traces formedin a die attach surface and a die having bumps attached to interconnectpads in an active surface; supporting the substrate and the die;dispensing a quantity of a curable adhesive on the substrate (coveringat least the connection sites on the traces) or on the active side ofthe die (covering at least the bumps); positioning the die with theactive side of the die toward the die attach surface of the substrate,and aligning the die and substrate and moving one toward the other sothat the bumps contact the corresponding traces (leads) on thesubstrate; applying a force to press the bumps onto the mating traces,sufficient to displace the adhesive from between the bump and the matingtrace; at least partially curing the adhesive; melting and thenre-solidifying the solder, forming a metallurgical interconnectionbetween the bump and the trace.

In another general aspect the invention features a method for formingflip chip interconnection, by providing a substrate having traces formedin a die attach surface and having a solder mask having openings overinterconnect sites on the leads, and a die having bumps attached tointerconnect pads in an active surface; supporting the substrate and thedie; positioning the die with the active side of the die toward the dieattach surface of the substrate, and aligning the die and substrate andmoving one toward the other so that the bumps contact the correspondingtraces (leads) on the substrate; melting and then re-solidifying to formthe interconnection between the bump and the trace.

In some embodiments the solder bump includes a collapsible solderportion, and the melt and solidifying step melts the bump to form theinterconnection on the lead. In some embodiments the substrate isfurther provided with a solder paste on the leads, and the step ofmoving the die and the substrate toward one another effects a contactbetween the bumps and the solder on the leads, and the melt andsolidifying step melts the solder on the lead to form theinterconnection.

In another general aspect the invention features a method for formingflip chip interconnection, by providing a substrate having traces formedin a die attach surface and having a solder mask having openings overinterconnect sites on the leads and having solder paste on the leads atthe interconnect sites, and a die having bumps attached to interconnectpads in an active surface; supporting the substrate and the die;positioning the die with the active side of the die toward the dieattach surface of the substrate, and aligning the die and substrate andmoving one toward the other so that the bumps contact the solder pasteon the corresponding traces (leads) on the substrate; melting and thenre-solidifying the solder paste, forming a metallurgical interconnectionbetween the bump and the trace.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic sketch of a portion of a conventionalbump-on-capture pad flip chip interconnection, in a sectional viewparallel to the plane of the package substrate surface, as indicated bythe arrows 1-1′ in FIG. 2;

FIG. 2 is a diagrammatic sketch showing a portion of a conventionalbump-on-capture pad flip chip interconnection, in a sectional viewperpendicular to the plane of the package substrate surface, asindicated by the arrows 2-2′ in FIG. 1;

FIG. 3 is a diagrammatic sketch showing a portion of anotherconventional bump-on-capture pad flip chip interconnection, in asectional view perpendicular to the plane of the package substratesurface;

FIG. 4 is a diagrammatic sketch of a portion of an embodiment of abump-on-lead flip chip interconnection according to the invention, in asectional view parallel to the plane of the package substrate surface;

FIG. 5 is a diagrammatic sketch showing a portion of an embodiment of abump-on-lead flip chip interconnection according to the invention as inFIG. 4, in a sectional view perpendicular to the plane of the packagesubstrate surface, as indicated by the arrows 6-6′ in FIG. 4;

FIG. 6 is a diagrammatic sketch of a portion of another embodiment of abump-on-lead flip chip interconnection according to the invention, in asectional view parallel to the plane of the package substrate surface;

FIG. 7 is a diagrammatic sketch showing a portion of an embodiment of abump-on-lead flip chip interconnection according to the invention as inFIG. 6, in a sectional view perpendicular to the plane of the packagesubstrate surface, as indicated by the arrows 7-7′ in FIG. 6;

FIGS. 8 and 9 are diagrammatic sketches, each of a portion of anotherembodiment of a bump-on-lead flip chip interconnection according to theinvention, in a sectional view parallel to the plane of the packagesubstrate surface;

FIGS. 10A-10C are diagrammatic sketches in a sectional view illustratingsteps in a process for making a flip chip interconnection according tothe invention;

FIGS. 11A-11D are diagrammatic sketches in a sectional view illustratingsteps in a process for making a flip chip interconnection according tothe invention;

FIG. 12 is a diagrammatic sketch showing a force and temperatureschedule for a process for making a flip chip interconnection accordingto the invention; and

FIG. 13 is a diagrammatic sketch in a sectional view showing abump-on-lead flip chip interconnection according to the invention,having composite bumps.

DETAILED DESCRIPTION OF THE DRAWINGS

The invention will now be described in further detail by reference tothe drawings, which illustrate alternative embodiments of the invention.The drawings are diagrammatic, showing features of the invention andtheir relation to other features and structures, and are not made toscale. For improved clarity of presentation, in the figures illustratingembodiments of the invention, elements corresponding to elements shownin other drawings are not all particularly renumbered, although they areall readily identifiable in all the figures.

The conventional flip chip interconnection is made by using a meltingprocess to join the bumps (conventionally, solder bumps) onto the matingsurfaces of the corresponding capture pads and, accordingly, this isknown as a “bump-on-capture pad” (“BOC”) interconnect. Two features areevident in the BOC design: first, a comparatively large capture pad isrequired to mate with the bump on the die; second, an insulatingmaterial, typically known as a “solder mask” is required to confine theflow of solder during the interconnection process. The solder maskopening may define the contour of the melted solder at the capture pad(“solder mask defined”), or the solder contour may not be defined by themask opening (“non-solder mask defined”); in the latter case—as in theexample of FIG. 1, described in more detail below—the solder maskopening may be significantly larger than the capture pad. The techniquesfor defining solder mask openings have wide tolerance ranges.Consequently, for a solder mask defined bump configuration, the capturepad must be large (typically considerably larger than the design sizefor the mask opening), to ensure that the mask opening will be locatedon the mating surface of the pad; and for a non-solder mask defined bumpconfiguration, the solder mask opening must be larger than the capturepad. The width of capture pads (or diameter, for circular pads) istypically about the same as the ball (or bump) diameter, and can be asmuch as two to four times wider than the trace width. This results inconsiderable loss of routing space on the top substrate layer. Inparticular, for example, the “escape routing pitch” is much bigger thanthe finest trace pitch that the substrate technology can offer. Thismeans that a significant number of pads must be routed on lowersubstrate layers by means of short stubs and vias, often beneath thefootprint of the die, emanating from the pads in question.

FIGS. 1 and 2 show portions 10, 20 of a conventional flip chip package,in diagrammatic sectional views; the partial sectional view in FIG. 1 istaken in a plane parallel to the package substrate surface, along theline 1-1′ in FIG. 2; and the partial sectional view in FIG. 2 is takenin a plane perpendicular to the package substrate surface, along theline 2-2′ in FIG. 1. Certain features are shown as if transparent, butmany of the features in FIG. 1 are shown at least partly obscured byoverlying features. Referring now to both FIG. 1 and FIG. 2, a dieattach surface of the package substrate includes a metal or layer formedon a dielectric layer 12. The metal layer is patterned to form leads 13and capture pads 14. A insulating layer 16, typically termed a “soldermask”, covers the die attach surface of the substrate; the solder maskis usually constructed of a photodefinable material, and is patterned byconventional photoresist patterning techniques to leave the matingsurfaces of the capture pads 14 exposed. Interconnect bumps 15 attachedto pads on the active side of the die 18 are joined to the matingsurfaces of corresponding capture pads 14 on the substrate to formappropriate electrical interconnection between the circuitry on the dieand the leads on the substrate. After the reflowed solder is cooled toestablish the electrical connection, an underfill material 17 isintroduced into the space between the die 18 and the substrate 12,mechanically stabilizing the interconnects and protecting the featuresbetween the die and the substrate.

As FIG. 1 shows by way of example, signal escape traces in the uppermetal layer of the substrate (leads 13), lead from their respectivecapture pads 14 across the die edge location, indicated by the brokenline 11, and away from the die footprint. In a typical example thesignal traces may have an escape pitch PE about 112 um. A 30 um/30 umdesign rule is typical for the traces themselves in a configuration asshown in FIG. 1; that is, the traces are nominally 30 um wide, and theycan be spaced as close together as 30 um. The capture pads are typicallythree times greater than the trace width and, accordingly in thisexample the capture pads have a width (or diameter, as they are roughlycircular in this example) nominally 90 um. And, in this example, theopenings in the solder mask are larger than the pads, having a nominalwidth (diameter) of 135 um.

FIGS. 1 and 2 show a non-solder mask defined solder contour. As thefusible material of the bumps on the die melt, the molten solder tendsto “wet” the metal of the leads and capture pads, and the solder tendsto “run out” over any contiguous metal surfaces that are not masked. Thesolder tends to flow along the contiguous lead 13, and here the solderflow is limited by the solder mask, for example at 19 in FIG. 1. Anon-solder mask defined solder contour at the pad is apparent in FIG. 2,in which the material of the bumps 15 is shown as having flowed, 29,over the sides of the capture pads 14 and down to the surface of thedielectric layer of the substrate 12. This is referred to as anon-solder mask defined contour because the solder mask does not limitthe flow of solder over the surface and down over the sides of thecapture pads, and—unless there is a substantial excess of solder at thepad—the flow of solder is limited by the fact that the dielectricsurface of the substrate is typically not wettable by the molten solder.A lower limit on the density of the capture pads in a conventionalarrangement, as in FIG. 1, is determined by, among other factors, limitson the capacity of the mask forming technology to make reliable narrowmask structures, and the need to provide mask structures betweenadjacent mask openings. A lower limit on the escape density isadditionally determined by, among other factors, the need for escapelines from more centrally located capture pads to be routed between moreperipherally located capture pads.

FIG. 3 shows a conventional solder mask defined solder contour, in asectional view similar to that in FIG. 2. A die 38 is shown affixed byway of bumps 35 onto the mating surfaces of capture pads 34 formed alongwith traces (leads 33) by patterning a metal layer on the die attachside of a dielectric layer of the substrate 32. After the reflowedsolder is cooled to establish the electrical connection, an underfillmaterial 37 is introduced into the space between the die 38 and thesubstrate 32, mechanically stabilizing the interconnects and protectingthe features between the die and the substrate. Here the capture pads 34are wider than in the example of FIGS. 1 and 2, and the solder maskopenings are smaller than the capture pads, so that the solder maskmaterial covers the sides and part of the mating surface each capturepad, as shown at 39, as well as the leads 33. When the bumps 35 arebrought into contact with the mating surfaces of the respective capturepads 34, and then melted, the solder mask material 36 restricts the flowof the molten solder, so that the shapes of the solder contours aredefined by the shapes and dimensions of the mask openings over thecapture pads 34.

FIGS. 4 and 6 each show a portion of a bump-on-lead (“BOL”) flip chipinterconnection according to an embodiment of the invention, in adiagrammatic partial sectional view taken in a plane parallel to thesubstrate surface, along the lines 4-4′ and 6-6′ in FIGS. 5 and 7,respectively. Certain features are shown as if transparent. According tothe invention the interconnection is achieved by mating the bumpsdirectly onto respective narrow leads or traces on the substrate and,accordingly, this is referred to herein as a “bump-on-lead” (“BOL”)interconnect. Solder mask materials typically cannot be resolved at suchfine geometries and, according to these embodiments of the invention, nosolder mask is used. Instead the function of confining molten solderflow is accomplished without a solder mask in the course of the assemblyprocess (as described below). FIG. 5 shows a partial sectional view of apackage as in FIG. 4, taken in a plane perpendicular to the plane of thepackage substrate surface, along the line 5-5′ in FIG. 4; and FIG. 7shows a partial sectional view of a package as in FIG. 6, taken in aplane perpendicular to the plane of the package substrate surface, alongthe line 7-7′ in FIG. 6.

Escape routing patterns for bump-on-lead (“BOL”) substrates according tothe invention are shown by way of example in FIGS. 4 and 6: in FIG. 4,arranged for a die on which the die attach pads for the interconnectballs are in a row near the die perimeter, the bumps 45 are mated ontocorresponding interconnect sites on the escape traces 43 in a row nearthe edge of the die footprint, indicated by the broken line 41; in FIG.6, arranged for a die on which the die attach pads are in an array ofparallel rows near the die perimeter, the bumps 65 are mated ontocorresponding interconnect sites on the escape traces 63 in acomplementary array near the edge of the die footprint, indicated by thebroken line 61.

As FIGS. 4 and 6 illustrate, the routing density achievable usingbump-on-lead interconnect according to the invention can equal thefinest trace pitch offered by the substrate technology. In the specificcase illustrated, this constitutes a routing density which isapproximately 90% higher than is achieved in a conventionalbump-on-capture pad arrangement. In the perimeter row embodiments of BOL(e.g., FIG. 4), the bumps are placed at a fine pitch, which can equalthe finest trace pitch of the substrate. This arrangement poses achallenge for the assembly process, because the bumping and bondingpitch must be very fine. In the perimeter array version of BOL (e.g.,FIG. 6), the bumps are arranged on an area array, providing greaterspace for a larger bumping and bonding pitch, and relieving thetechnological challenges for the assembly process. Even in the arrayembodiments, the routing traces on the substrate are at the sameeffective pitch as in the perimeter row arrangement, and an arrangementas in FIG. 6 relieves the burden of fine pitch bumping and bondingwithout sacrificing the fine escape routing pitch advantage.

Referring particularly now to FIGS. 4 and 5, leads 43 are formed bypatterning a metal layer on a die attach surface of a substratedielectric layer 42. According to the invention, electricalinterconnection of the die 48 is made by joining the bumps 45 on the diedirectly onto the leads 43. No capture pads are required according tothe invention and, in embodiments as in FIGS. 4 and 5, no solder mask isrequired; the process is described in detail below.

Conventional capture pads typically are about the same width (diameter)as the bumps, and are typically two to four times as wide as the traceor lead width. As will be appreciated, some variation in the width ofleads is expected. As used herein, a variation in trace width of as muchas 120% of the nominal or trace design rule width does not constitute acapture pad, and bump-on-lead interconnection according to the inventionincludes bumps formed on such wider portions of leads.

Similarly, referring to FIGS. 6 and 7, leads 63 are formed by patterninga metal layer on a die attach surface of a substrate dielectric layer62. The signal escape traces lead across the die edge location,indicated by the broken line 61, and away from the die footprint.According to the invention, electrical interconnection of the die 68 ismade by joining the bumps 65 on the die directly onto the leads 63.Certain of the escape traces, e.g. 66, leading across the die edgelocation from interconnect sites in rows toward the interior of the diefootprint, pass between the bumps 65 on more peripheral rows ofinterconnect sites. No capture pads are required according to theinvention and, in embodiments as in FIGS. 6 and 7, no solder mask isrequired; the process is described in detail below.

As FIGS. 4 and 6 illustrate, bump-on-lead interconnect according to theinvention can provide a significantly higher signal trace escape routingdensity. Also, as FIGS. 4 and 6 illustrate, the BOL interconnectaccording to this aspect of the invention does not require use of asolder mask to define the solder contour at the interconnect site.

The BOL interconnection structure of embodiments such as are shown byway of example in FIGS. 4, 5, 6 and 7 can be produced according to theinvention by any of several methods, not requiring a solder mask. Ingeneral, interconnect bumps (typically solder bumps) are affixed ontointerconnect pads on the active side of the die. A die attach surface ofthe substrate (termed the “upper” surface) has an upper metal layerpatterned to provide the traces as appropriate for interconnection withthe arrangement of bumps on the particular die. Because no capture padsare required, the patterned traces (leads) need only route through sitescorresponding to a pattern complementary to the arrangement of bumps onthe die. In a preferred method of the invention, an encapsulating resinadhesive is employed to confine the solder flow during a melt phase ofthe interconnection process.

FIGS. 8 and 9 show two examples of a portion of a bump-on-lead flip chipinterconnection according to other embodiments of the invention, in adiagrammatic sectional view taken in a plane parallel to the substratesurface. Certain features are shown as if transparent. According to thisaspect of the invention a solder mask is provided, which may have anominal mask opening diameter in the range about 80 um to 90 um. Soldermask materials can be resolved at such pitches and, particularly,substrates can be made comparatively inexpensively with solder maskshaving 90 um openings and having alignment tolerances plus or minus 25um. In some embodiments laminate substrates (such as 4 metal layerlaminates), made according to standard design rules, are used. In theembodiments of FIGS. 8 and 9, for example, the traces may be at ˜90 umpitch and the interconnection sites may be in a 270 um area array,providing an effective escape pitch ˜90 um across the edge of the diefootprint, indicated by the broken line 81.

In embodiments as in FIGS. 8 and 9 a no-flow underfill is not required;a conventional capillary underfill can be employed.

In embodiments as in FIG. 8 the interconnection is achieved by matingthe bumps directly onto an interconnect site 84 on a narrow lead ortrace 83 patterned on a dielectric layer on the die attach surface ofthe substrate 82; there is no pad, and the solder mask 86 serves tolimit flow of solder within the bounds of the mask openings 88,preventing solder flow away from the interconnect site along thesolder-wettable lead. The solder mask may additionally confine flow ofmolten solder between leads, or this may be accomplished in the courseof the assembly process.

In embodiments as in FIG. 9, as in FIG. 8, there are, according to theinvention, no interconnect pads. Narrow leads or traces 93 patterned ona dielectric layer on the die attach surface of the substrate 92. Solderpaste is provided at the interconnect sites 94 on the leads 93, toprovide a fusible medium for the interconnect. The openings 98 in thesolder mask 96 serve to define the paste. The paste is dispensed, forexample by a standard printing process, then is reflowed, and then maybe coined if necessary to provide uniform surfaces to meet the balls.The solder paste can be applied in the course of assembly using asubstrate as described above with reference to FIG. 8; or, a substratemay be provided with paste suitably patterned prior to assembly. Otherapproaches to applying solder selectively to the interconnect sites maybe employed in the solder-on-lead embodiments of the invention,including electroless plating and electroplating techniques. Thesolder-on-lead configuration provides additional solder volume for theinterconnect, and can accordingly provide higher product yield, and canalso provide a higher die standoff.

Accordingly, in some embodiments the solder-on-lead configurationaccording to the invention is employed for interconnection of a diehaving high-melting temperature solder bumps (such as a high-leadsolder, conventionally used for interconnection with ceramic substrates)onto an organic substrate. The solder paste can be selected to have amelting temperature low enough that the organic substrate is not damagedduring reflow. To form the interconnect in such embodiments thehigh-melting interconnect bumps are contacted with the solder-on-leadsites, and the remelt fuses the solder-on-lead to the bumps. Where anoncollapsible bump is used, together with a solder-on-lead process, nopreapplied adhesive is required, as the displacement or flow of thesolder is limited by the fact that only a small quantity of solder ispresent at each interconnect, and the noncollapsible bump preventscollapse of the assembly.

In other embodiments the solder-on-lead configuration according to theinvention is employed for interconnection of a die having eutecticsolder bumps.

One embodiment of a preferred method for making a bump-on-leadinterconnection is shown diagrammatically in FIGS. 10A-10C.

Referring to the figures, a substrate 112 is provided, having at leastone dielectric layer and having a metal layer on a die attach surface113, the metal layer being patterned to provide circuitry, particularlytraces or leads 114 having sites for interconnection, on the die attachsurface. The substrate 112 is supported, for example on a carrier orstage 116, with a substrate surface 111 opposite the die attach surface113 facing the support. A quantity of an encapsulating resin 122 isdispensed over the die attach surface 113 of the substrate, covering atleast the interconnect sites on the leads 114. A die 102 is provided,having bumps 104 attached to die pads (not shown in the figure) on theactive side 103. The bumps include a fusible material which contacts themating surfaces of the leads. A pick-and-place tool 108 including achuck 106 picks up the die by contact of the chuck 106 with the backside101 of the die. Using the pick-and-place tool, the die is positionedfacing the substrate with the active side of the die toward the dieattach surface of the substrate, as shown in FIG. 10A; and the die andsubstrate are aligned and moved one toward the other (arrow M) so thatthe bumps 104 contact the corresponding interconnect sites on the traces(leads) 114 on the substrate. Then a force is applied (arrow F) to pressthe bumps 105 onto the mating surfaces 134 at the interconnect sites onthe leads 115, as shown in FIG. 10B. The force must be sufficient atleast to displace the adhesive 122 from between the bumps and the matingsurfaces at the interconnect sites on the leads 154. The bumps may bedeformed by the force, breaking the oxide film on the contacting surfaceof the bumps and/or on the mating surface of leads. The deformation ofthe bumps may result in the fusible material of the bumps being pressedonto the top and over the edges of the lead. The adhesive is caused tocure at least partially, as shown at 132, as for example by heating to aselected temperature. At this stage the adhesive need only be partiallycured, that is, only to an extent sufficient subsequently to preventflow of molten solder along an interface between the adhesive and theconductive traces. Then the fusible material of the bumps 105 is meltedand then is re-solidified, forming a metallurgical interconnectionbetween the bump 105 and lead 115, and the adhesive curing is completed,to complete the die mount and to secure the electrical interconnectionat the mating surface (now an interconnect interface) 144, as showngenerally at 140 in FIG. 10C. In the plane of the sectional view shownin FIG. 10C, interconnection is formed between certain of the bumps 145and corresponding interconnect sites on certain of the leads 155, as forexample in a configuration as in FIG. 6. Other leads 156 areinterconnected at other localities, which would be visible in othersectional views. A comparatively high trace density is shown. The curingof the adhesive 142 may be completed prior to, or concurrently with, orfollowing melting the solder. Typically, the adhesive is a thermallycurable adhesive, and the extent of curing at any phase in the processis controlled by regulating the temperature. The components can beheated and cured by raising the temperature of the chuck on the pick andplace tool, or by raising the temperature of the substrate support, forexample.

The process is shown in further detail in FIGS. 11A-11D. In FIG. 11A, asubstrate 212 is provided on a die attach surface with conductive(metal) traces 214, and interconect sites on the traces are covered withan adhesive 222. The die 202 is positioned in relation to the substrate212 such that the active side of the die faces the die attach side ofthe substrate, and is aligned (arrows A) such that bumps 204 on the dieare aligned with corresponding mating surfaces on traces 214. The dieand the substrate are moved toward one another so that the bumps contactthe respective mating surfaces on the traces. Then as shown in FIG. 11Ba force is applied to move the bumps 205 and traces 215 against oneanother, displacing the adhesive as shown at 232 in FIG. 11B, anddeforming the bumps onto the mating surfaces 234 and over the edges ofthe traces. Deformation of the bumps on the traces breaks the oxide filmon the contact surfaces of the bumps and the mating surfaces of thetraces, establishing a good electrical connection, and deformation ofthe bumps over the edges of the traces helps establish a good temporarymechanical connection. As in the example of FIG. 10A-10C, theinterconnect sites of certain of the traces 216 are out of the plane ofFIG. 11B. Heat is applied to partially cure the adhesive as shown at 236in FIG. 11C. Then heat is applied to raise the temperature of the bumpssufficiently to cause the fusible material of the bumps to melt, asshown in FIG. 11D. This substantially (though not necessarily fully)completes the cure of the adhesive 246 and completes the metallurgicalinterconnection of the bumps 245 onto the mating surfaces 244 at theinterconnect sites on the leads 215. The cured adhesive stabilizes thedie mount.

In an alternative embodiment of a preferred method, the adhesive can bepre-applied to the die surface, or at least to the bumps on the diesurface, rather than to the substrate. The adhesive can, for example, bepooled in a reservoir, and the active side of the die can be dipped inthe pool and removed, so that a quantity of the adhesive is carried onthe bumps; then, using a pick-and-place tool, the die is positionedfacing a supported substrate with the active side of the die toward thedie attach surface of the substrate, and the die and substrate arealigned and moved one toward the other so that the bumps contact thecorresponding traces (leads) on the substrate. Such a method isdescribed in U.S. Pat. No. 6,780,682, Aug. 24, 2004, which is herebyincorporated by reference. Then forcing, curing, and melting are carriedout as described above.

A force and temperature schedule for a process according to theinvention is shown diagrammatically by way of example in FIG. 12. Inthis chart, time runs from left to right on the horizontal axis; a forceprofile 310 is shown as a thick solid line, and a temperature profile320 is shown as a dotted line. The temperature profile begins at atemperature in the range about 80° C.-about 90° C. The force profilebegins at essentially zero force. Beginning at an initial time t_(i) theforce is rapidly (nearly instantaneously) raised 312 from F_(i) to adisplacement/deformation force F_(d) and held 314 at that force for atime, as discussed below. F_(d) is a force sufficiently great todisplace the adhesive away from between the bumps and the matingsurfaces of the leads; and, preferably, sufficient to deform the fusible(lead-contacting) portion of the bumps onto the mating surface, breakingthe oxide films and forming a good metal-to-metal (metallurgical)contact, and, in some embodiments, over the edges of the leads toestablish a mechanical interlock of the bumps and the leads (“creep”deformation). The total amount of force required will depend upon thebump material and dimensions and upon the number of bumps, and can bedetermined without undue experimentation. As the force is raised, thetemperature is also rapidly raised 322 from an initial temperature T_(i)to a gel temperature Tg. The gel temperature Tg is a temperaturesufficient to partially cure the adhesive (to a “gel”). Preferably, theforce and temperature ramps are set so that there is a short lag timet_(def), following the moment when F_(d) is reached and before T_(g) isreached, at least long enough to permit the elevated force to displacethe adhesive and to deform the bumps before the partial cure of theadhesive commences. The assembly is held 314, 324 at thedisplacement/deformation pressure F_(d) and at the gel temperature T_(g)for a time t_(gel) sufficient to effect the partial cure of theadhesive. The adhesive should become sufficiently firm that it cansubsequently maintain a good bump profile during the solder remeltphase—that is, sufficiently firm to prevent undesirable displacement ofthe molten fusible material of the bump, or flow of the molten fusiblematerial along the leads. Once the adhesive has partially cured to asufficient extent, the pressure may be ramped down rapidly 318 tosubstantially no force (weight of the components). The temperature isthen rapidly raised further 323 to a temperature T_(m) sufficient toremelt the fusible portions (solder) of the bumps, and the assembly isheld 325 at the remelt temperature T_(m) for a time t_(melt/cure) atleast sufficient to fully form the solder remelt on the traces, andpreferably sufficient to substantially (though not necessarily fully)cure the adhesive. Then the temperature is ramped down 328 to theinitial temperature T_(i), and eventually to ambient. The processoutlined in FIG. 12 can run its course over a time period of 5-10seconds.

The adhesive in embodiments as in FIG. 12 may be referred to as a“no-flow underfill”. In some approaches to flip chip interconnection,the metallurgical interconnection is formed first, and then an underfillmaterial is flowed into the space between the die and the substrate. The“no-flow underfill” according to the invention is applied before the dieand the substrate are brought together, and the no-flow underfill isdisplaced by the approach of the bumps onto the leads, and by theopposed surfaces of the die and the substrate. The adhesive for theno-flow underfill adhesive according to the invention is preferably afast-gelling adhesive—that is, a material that gels sufficiently at thegel temperature in a time period in the order of 1-2 seconds. Preferredmaterials for the no-flow underfill adhesive include, for example,so-called non-conductive pastes, such as those marketed by ToshibaChemicals and by Loktite-Henkel, for example.

Alternative bump structures may be employed in the bump-on-leadinterconnects according to the invention. Particularly, for example,so-called composite solder bumps may be used. Composite solder bumpshave at least two bump portions, made of different bump materials,including one which is collapsible under reflow conditions, and onewhich is substantially non-collapsible under reflow conditions. Thenon-collapsible portion is attached to the interconnect site on the die;typical conventional materials for the non-collapsible portion includevarious solders having a high lead (Pb) content, for example. Thecollapsible portion is joined to the non-collapsible portion, and it isthe collapsible portion that makes the connection with the leadaccording to the invention. Typical conventional materials for thecollapsible portion of the composite bump include eutectic solders, forexample.

An example of a bump-on-lead interconnect employing a composite bump isshown in a diagrammatic sectional view in FIG. 13. Referring now to FIG.13, die 302 is provided on die pads in the active side of the die withcomposite bumps 344 that include a noncollapsible portion 345 and acollapsible portion 347. The collapsible portion may be, for example, aeutectic solder or a relatively low temperature melt solder). Thecollapsible portion contacts the mating surface of the lead and, wheredeformation of the fusible portion of the bump over the lead 355 isdesired, the collapsible portion of the bump is deformable under theconditions of force employed. The noncollapsible portion may be, forexample, a solder having a high lead (Pb) content. The noncollapsibleportion does not deform when the die is moved under pressure against thesubstrate 312 during processing, and does not melt during the reflowphase of the process. Accordingly the noncollapsible portion can bedimensioned to provide a standoff distance between the active surface ofthe die and the die attach surface of the substrate.

As may be appreciated, the bumps in embodiments as shown in, forexample, FIGS. 4, 5, 6 and 7 need not necessarily be fully collapsiblebumps. The structures shown in those FIGs. may alternatively be madeusing composite bumps, or using a solder-on-lead method, as describedabove.

Other embodiments are within the following claims.

What is claimed:
 1. A method of making a semiconductor device,comprising: providing a substrate; forming a trace including aninterconnect site over a surface of the substrate; providing a firstsemiconductor die; and forming an interconnect structure including awidth greater than a width of the interconnect site between the firstsemiconductor die and the interconnect site.
 2. The method of claim 1,wherein the width of the interconnect site is less than or equal to 120%of a width of the trace away from the interconnect site.
 3. The methodof claim 1, further including forming the interconnect structureincluding a collapsible portion and a non-collapsible portion.
 4. Themethod of claim 1, wherein the substrate includes a second semiconductordie.
 5. The method of claim 1, wherein the substrate includes a printedcircuit board.
 6. The method of claim 1, further including forming aninsulating layer over the surface of the substrate.
 7. A method ofmaking a semiconductor device, comprising: providing a substrate;forming a trace including an interconnect site over a surface of thesubstrate; and disposing a composite interconnect structure including acollapsible portion and a non-collapsible portion over the interconnectsite of the trace.
 8. The method of claim 7, further including formingan insulating layer including an opening disposed over the interconnectsite over the trace.
 9. The method of claim 7, further including formingthe interconnect site of the trace including a width less than a widthof the composite interconnect structure.
 10. The method of claim 7,wherein the substrate includes a printed circuit board.
 11. The methodof claim 7, wherein the substrate includes a semiconductor die.
 12. Themethod of claim 7, further including: providing a first semiconductordie; and forming the composite interconnect structure over a surface ofthe first semiconductor die.
 13. The method of claim 12, wherein thesubstrate includes a second semiconductor die.
 14. A semiconductordevice, comprising: a substrate; a trace including an interconnect siteformed over the substrate; and an interconnect structure including awidth greater than a width of the interconnect site of the tracedisposed over the interconnect site of the trace.
 15. The semiconductordevice of claim 14, wherein the width of the interconnect site is lessthan or equal to 120% of a width of the trace away from the interconnectsite.
 16. The semiconductor device of claim 14, wherein the interconnectstructure includes a non-collapsible portion and a collapsible portion.17. The semiconductor device of claim 14, wherein the substrate includesa printed circuit board.
 18. The semiconductor device of claim 14,wherein the substrate includes a semiconductor die.
 19. Thesemiconductor device of claim 14, further including a firstsemiconductor die disposed over the interconnect structure.
 20. Thesemiconductor device of claim 19, wherein the substrate includes asecond semiconductor die.
 21. A semiconductor device, comprising: asubstrate; a trace formed over the substrate; and an interconnectstructure disposed over an interconnect site of the trace.
 22. Thesemiconductor device of claim 21, wherein the interconnect site of thetrace includes a width less than a width of the interconnect structure.23. The semiconductor device of claim 21, wherein the substrate includesa semiconductor die.
 24. The semiconductor device of claim 21, furtherincluding a first semiconductor die disposed over the interconnectstructure.
 25. The semiconductor device of claim 24, wherein thesubstrate includes a second semiconductor die.